A number of different standards and technologies for operating wireless telephones exist today. In order to operate properly, a wireless telephone must be within the boundaries of a wireless telephone system that supports the same technology and is able to operate at the same frequency as the wireless telephone. As a result, dual mode wireless telephones exist today that are designed for use in more than one wireless telephone system. For example, a wireless telephone that operates in both an Advanced Mobile Phone Service ("AMPS") mode and a Global System for Mobile Communication ("GSM") mode is known. The object of such dual mode combinations is generally to enable the user to transfer a wireless telephone outside of their home service area and increase the probability that the wireless telephone will continue to have wireless service available.
FIG. 1 is a schematic diagram of data transmission flow in a known dual mode wireless device operable in either the AMPS mode or the GSM mode. As illustrated in FIG. 1, a dual mode wireless device, such as a wireless telephone, includes a controller circuit 200 and a transmitter circuit 202 connected along a bus 204. Both analog and digital data signals, corresponding to voice and data, are input from a microphone 206 and an interface 208 of a computer device, for example, to a data source 210 located at the controller circuit 200. When the dual mode wireless device is operated in an AMPS mode, the analog signals from the microphone 206 are converted to digital data by an A/D converter 214 located in the AMPS unit 212, and added to the digital data input to the data source 210 by the interface 208 of the computer device using an adder 216. The resulting added signals output by the adder 216 are received by an input register 218 located within a digital signal processor 220 of the controller circuit 200.
On the other band, when the wireless telephone is operated in the GSM mode, the analog signals output by the data source 210 after being received from the microphone 206 are converted to digital data signals by an A/D converter 224 located in a GSM unit 222, and both the digital data signals input by the data source 210 from interface 208 of the computer device and the digital data signals output from the A/D converter 224 are sent to an interleaver 226 of the GSM unit 222. The interleaver 226 interleaves the digital data signals according to GSM protocol, and outputs the interleaved data signals to the input register 218 of the digital signal processor 220.
Depending upon whether the device is being operated in the AMPS or the GSM mode, the digital data signals are transferred from the input register 218 to a microprocessor 228 of the digital signal processor 220 to be packaged and buffered to form processed data that is then output from the digital signal processor 220 to an output register 230 of the controller circuit 200. The processed data is held in the output register 230 until a new piece of data is required by the transmitting circuit 202, at which time the processed data is transferred from the output register 230 of the controller circuit 200 to the bus 204 connecting the controller circuit 200 to the transmitter circuit 202. The processed data is transferred along the bus 204 to an input register 232 of the transmitter circuit 202 and is transferred from the input register 232 to an interpolator 234. The interpolator 234 interpolates the processed data and outputs the resulting interpolated data to a modulator 236. The modulator 236 modulates the interpolated data, and the resulting modulated data is then output by the transmitter circuit 202 through an antenna (not shown).
In the prior art dual mode wireless telephone of FIG. 1, each time the transmitter circuit 202 requests a packet of data from the controller circuit 200, the requested data packet must be generated by the signal processor 220 and transported along the bus 204 from the output register 230 of the controller circuit 200 to the input register 232 of the transmitter circuit 202. As a result, each time the transmitter circuit 202 requests a packet of data from the controller circuit 200, current processing from the signal processor 220 must be interrupted to enable the signal processor 220 to generate the data packet. As the rate of these interruptions increases, a bottleneck tends to form both between the signal processor 220 and the output register 230 of the controller circuit 200 and along the bus 204 between the controller circuit 200 and the transmitter circuit 202, corrupting reliability of the data transmission. This bottleneck results from noise that is caused from high clock rates at the bus 204, which desensitize the receiver receiving the output from the transmitter circuit 202, and from high current drain in MIPS (million instructions per second) between the digital signal processor 220 and the output register 230, which lowers the battery life of the device.
One method available to reduce the interrupt rate to the digital signal processor 220 caused by the requests for data from the transmitter circuit 202 is for the digital signal processor 220 to generate a large set of data and create a buffer at output register 230 from which the transmitter circuit 202 draws data in real time. As a result, the interruptions of the digital signal processor 220 are reduced, occurring only when the buffer required additional data. This buffer method reduces the interrupt rate to the digital signal processor 220, allowing more efficient operation so that lower MIPS are required by the digital signal processor 220, reducing current drain on the battery and increasing battery life. However, not all supported integrated circuits include the necessary buffer capacity built into the controller circuit 200.
In addition, the signal from the interpolator 234 could be pre-distorted using analog components in the present state of the art, in order to reduce the effects of distortion caused by bandwidth limitations in the modulator unit 236. To achieve analog pre-distortion and to achieve modulated signal accuracy and cleanliness, active operational amplifiers, switches, and extra inductors and capacitors may need to be added to the transmitter circuit 202 to obtain the required accuracy. These support circuits increase the size and cost of the transmitter circuit so that such as approach would be difficult and costly using current technology. In addition, even if support was available on the transmitter circuit 202, the higher data rate involved in transporting the high speed data from the output register 230 across the bus 204 to the input register 232 of the transmitter circuit 202 would cause radio interference back through the antenna, causing the radio to be de-sensitized.
Accordingly, what is needed is dual mode wireless telephone device that minimizes bottlenecks by reducing an interrupt rate of the signal processor while at the same time reducing interference in neighboring bands.